设为首页 设为首页 加入收藏 加入收藏 网站地图
[请登陆][免费注册]
搜 索

您的位置 :首页  新闻产业观察
克服大批量生产的薄片检测挑战
                   0
出自:SEMI中国

By Philippe Gastaldo, Product and R&D Director, UnitySC
 
As the automotive electronics market continues to grow, spurred by developments such as semi-autonomous and fully autonomous vehicles, the demand is increasing for power semiconductor components with sophisticated conversion schemes that decrease power consumption and heat. To address these needs, power semiconductor manufacturers are turning to thin wafers.
 
Today’s power semiconductors are manufactured primarily on 200mm wafers that range in thickness from 50 to 100μm, but their roadmaps are targeting wafers as thin as 1μm. These wafers are thinned on the backside by mechanical polishing. Defects resulting from the polishing process include grinding marks, grinding failures resulting in edge chips, star cracks and comets formed by edge particles that get caught in the grinding wheel, embedded particles, cleavage lines and a variety of other imperfections.
 
Because these defects often appear on the wafer backside rather than the active side, they are not as much of an issue for thicker wafers. But as wafers become increasingly thinner, these defects are affecting chip reliability. While the backside defects in thinned wafers don’t initially impede the chip’s functionality, they do impact the device’s overall reliability. In fact, a power semiconductor can easily be processed through to final packaging without detecting the defects. However, when subjected to the high temperatures of an automotive application, for example, a crack can form and lead to chip failure.
 
While thin-wafer inspection has become critically important for the wafer-sorting process, as well as helping engineers improve thinning processes themselves, many of the existing technologies are limited and inadequate for detecting defects.
 
Most of today’s defect inspection is done manually, by visual inspection, using a powerful light, but without magnification. As this process is often performed by different operators, it’s not repeatable, and results in minimal defect information that lacks accurate classification.
 
Automated optical inspection that uses a camera with magnification has also been tried, without success, because while it provides an automated and repeatable process, it is not capable of inspecting the wafer topography to distinguish between grinding marks and deep cracks.
 
Some have considered darkfield inspection an option for detecting defects in thin wafers. Based on optical technology, darkfield is the measurement of light reflected at a lower angle. While darkfield is useful for front-end inspection, backside grinding renders it ineffective due to the resulting wafer-surface roughness. As a result, darkfield inspection should be avoided following backside grinding.
 
Optimal thin-wafer inspection requires a technology that is sensitive to nanotopography and that can both detect and measure surface variations of nanometric proportions. Interferometry, a measurement method using the phenomenon of interference of light, radio or sound waves1, is capable of this, but many tools based on interferometry are slow and expensive with low throughput. Additionally, while interferometry is an excellent option for some surface inspection applications, it is not suitable for inspecting and sorting thin wafers in a high-volume manufacturing environment.
 
Alternatively, there is a technology known as phase-shift deflectometry (PSD) that measures the wafer surface topography by imaging through the surface and generating a pattern on the tool display. Topography variation on the surface changes the shape of the pattern, which indicates the presence of a defect. By generating images of the topography map, pitch analysis can be performed to accurately classify the defect while providing its size and depth. Used until recently for Silicon on Insulator (SOI) and Epitaxial (EPI) wafer inspection and slip line detection, PSD is gaining traction for wafer thinning inspection.
 
Companies that work with ultra-thin wafers are beginning to employ PSD technology that is both cost-effective and fast enough for high-volume manufacturing. Additionally, some companies are beginning to integrate automatic classification software that provides accurate and detailed defect information. This approach, with its advantages over the predominant visual inspection currently being employed by most manufacturers, is expected to become the preferred method for thin-wafer inspection—particularly in power semiconductor applications for mission-critical applications like automotive. UnitySC is pioneering this approach with its 4See Series and Deflector module.

 

 

0
                   0
文章收入时间: 2017-09-20
相关信息
京东与中石化合作30000家智能加油站 布局智慧门店 2017-10-18
英媒称中国将成人工智能超级大国 远远甩开美国 2017-10-18
AI纳米机器人或将在20年内植入人体,人类拥有超能力还会远吗? 2017-10-18
简评亚洲人工智能发展现状:机遇与挑战并存 2017-10-18
研究显示AI正创造更多工作岗位 2017-10-18
PC市场明年势必重回增长 中国和俄罗斯是主要推动力 2017-10-18
全球硅晶圆供应告急!12英寸99%依赖进口,晶圆自给任重道远! 2017-10-18
高通完成芯片5G数据连接 5G手机明年可待 2017-10-18
格芯推出新型汽车半导体平台,助力未来互联汽车发展 2017-10-18
麦格理:看好中国半导体市场 予华虹半导体目标价16元 2017-10-18
 
SEMI简介 | About SEMI | 联系我们 | Privacy Policy | semi.org
上海集成电路协会 | 中国电子报 | 赛迪网半导体 | 电子产品世界 | 中电网 | 中国电子材料网
Copyright © 2017 SEMI®. All rights reserved.
沪ICP备06022522号
沪公网安备31011502000679号